Fujitsu's Monaka Pairs TSMC 2nm Cores With 5nm Dies for HPC
Monaka keeps FP64 and general-purpose cores in view while its designers treat the most advanced process as necessary only for the logic that needs it, which separates the chip's priorities from AI-specialized designs.
Reporting from 1 source: ASCII.jp.
Fujitsu's Arm-based server CPU Monaka, successor to the A64FX, targets HPC with a 144-core design split across four pairs of core dies. The core dies use TSMC's N2P process while the SRAM and IO dies use 5nm, stacked on a silicon interposer. Monaka carries DDR5-8000 memory across 12 channels and a 256-bit SVE2 implementation. FP64 support is in scope; NVLink Fusion is deferred to the next-generation Monaka-X.
Fujitsu laid out the split behind Monaka at Hot Chips: core dies on TSMC N2P, SRAM and IO dies on 5nm, four pairs of core dies stacked on SRAM dies and wired through a silicon interposer. The reasoning is that SRAM density plateaus from around 5nm, so pushing the smallest node onto cache and register files buys little while raising manufacturing cost. The 144 cores work out to 36 per die. Memory is DDR5-8000 across 12 channels, which the presentation acknowledges is modest by current standards.
Synthesized by Yomimono from the 1 cited source below, including Japanese-language reporting where cited, then editorially reviewed before publishing.